Field of the Invention
The present invention relates to a solid-state imaging apparatus and an endoscope apparatus using the solid-state imaging apparatus. Priority is claimed on Japanese Patent Application No. 2014-097011, filed on May 8, 2014, the content of which is incorporated herein by reference.
Description of Related Art
A complementary metal-oxide semiconductor (CMOS) type solid-state imaging apparatus is known as a solid-state imaging apparatus. As an example of the CMOS type solid-state imaging apparatus, a configuration in which noise occurring in a pixel section is reduced for implementing high image quality is disclosed in the publication of Japanese Patent No. 4403387. First, a configuration and an operation of the solid-state imaging apparatus disclosed in the publication of Japanese Patent No. 4403387 will be described.
FIG. 15 shows a configuration example of a conventional solid-state imaging apparatus 200. As shown in FIG. 15, the solid-state imaging apparatus 200 has a pixel 11A, a load transistor 31, and a fixed transistor 32. In the solid-state imaging apparatus 200, a plurality of pixels 11A are disposed in a matrix. In FIG. 15, one pixel 11A is shown. The pixel 11A has a photodiode 21, a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25.
The photodiode 21 generates a signal charge according to an amount of an incident light. The transfer transistor 22 transfers the signal charge generated by the photodiode 21 to floating diffusion FD. The operation of the transfer transistor 22 is controlled by a transfer pulse TRF supplied to transfer wiring 26. The reset transistor 23 resets the signal charge accumulated in the floating diffusion FD. The operation of the reset transistor 23 is controlled by a reset pulse RST supplied to reset wiring 28. The amplification transistor 24 amplifies a signal according to the signal charge accumulated in the floating diffusion FD. The selection transistor 25 selects a signal output from the amplification transistor 24 and outputs the selected signal to a vertical signal line 121. The operation of the selection transistor 25 is controlled by a selection pulse SEL supplied to selection wiring 29.
A load transistor 31 and a fixed transistor 32 are connected to the vertical signal line 121. The operation of the load transistor 31 is controlled by a load pulse LOAD. The operation of the fixed transistor 32 is controlled by a fixed pulse FIX.
FIG. 16 shows an operation example of the solid-state imaging apparatus 200. In FIG. 16, waveforms of the load pulse LOAD, the fixed pulse FIX, the selection pulse SEL, the reset pulse RST, and the transfer pulse TRF are shown. In addition, in FIG. 16, a potential of the vertical signal line 121 is shown. The horizontal direction of FIG. 16 represents time and the vertical direction of FIG. 16 represents a voltage.
A source of the fixed transistor 32 is connected to the vertical signal line 121. A drain of the fixed transistor 32 is connected to a voltage Vmid (1.5 V). The voltage Vmid is a voltage lower than a power supply voltage VDD. Before the operation of the pixel 11A of a certain row ends and the operation of the pixel 11A of the next row starts (before the reset operation is performed) in the solid-state imaging apparatus 200, the fixed pulse FIX changes from a Low level to a High level and therefore the fixed transistor 32 is in an ON state. Thereby, a potential of the vertical signal line 121 becomes Vmid.
Thereafter, the operation of the pixel 11A of the next row starts. The load pulse LOAD changes from the Low level to the High level and therefore the load transistor 31 is in the ON state. Simultaneously, the selection pulse SEL changes from the Low level to the High level and therefore the selection transistor 25 is in the ON state. Simultaneously, the reset pulse RST changes from the Low level to the High level and therefore the reset transistor 23 is in the ON state. Thereby, the signal charge accumulated in the floating diffusion FD is reset.
Thereafter, the reset pulse RST changes from the High level to the Low level and therefore the reset transistor 23 is in an OFF state. Thereby, a signal of the reset level is output to the vertical signal line 121. Thereafter, the transfer pulse TRF changes from the Low level to the High level and therefore the transfer transistor 22 is in the ON state. Thereby, the signal charge generated by the photodiode 21 is transferred to the floating diffusion FD.
Thereafter, the transfer pulse TRF changes from the High level to the Low level and therefore the transfer transistor 22 is in the OFF state. Thereby, the signal of the signal level is output to the vertical signal line 121. Thereafter, the load pulse LOAD changes from the High level to the Low level and therefore the load transistor 31 is in the OFF state. Simultaneously, the selection pulse SEL changes from the High level to the Low level and therefore the selection transistor 25 is in the OFF state. Thereafter, the fixed pulse FIX changes from the High level to the Low level and therefore the fixed transistor 32 is in the OFF state.
After the potential of the vertical signal line 121 changes from 0 V to a voltage Vmid in the above-described operation, the signal of the reset level is output to the vertical signal line 121. On the other hand, when there is no fixed transistor 32, the potential of the vertical signal line 121 changes from 0 V to the reset level when the signal of the reset level has been output to the vertical signal line 121. Thus, as compared with when there is no fixed transistor 32, a change in the potential of the vertical signal line 121 due to the reset operation is reduced in period T1 of FIG. 16.
Because the fixed transistor 32 is provided in the solid-state imaging apparatus 200, a change (shaking) in the potential of a well of a pixel capacitively coupled by the vertical signal line 121 and parasitic capacitance is suppressed. Accordingly, noise or shading caused as a result of the change (shaking) in the well potential of the pixel is reduced.
In the conventional solid-state imaging apparatus 200, a scheme of reading signals by driving pixels in units of rows is applied. In this scheme, an operation shown in FIG. 16 is simultaneously performed on all pixels disposed in the same row. In period T11 of FIG. 16, the signal of the reset level output to the vertical signal line 121 of each column is sequentially read in the horizontal direction for every column of the array of the pixels. Likewise, in period T12 of FIG. 16, the signal of the signal level output to the vertical signal line 121 of each column is sequentially read in the horizontal direction for every column of the array of the pixels. That is, between read operations on the signal of the reset level and the signal of the signal level of the same pixel, signals of reset levels or signal levels of a plurality of other pixels are read.
In the above-described scheme, there is a time difference of several μs between a read timing of the signal of the reset level and a read timing of the signal of the signal level of the same pixel. Thus, when the power supply voltage VDD has changed (shaken) between the timings at a low frequency, noise (an error) may be superimposed on a signal output from the pixel as a result of the change. Hereinafter, details will be described.
FIG. 17 shows an operation example when the power supply voltage VDD has changed (shaken) in the conventional solid-state imaging apparatus 200. In FIG. 17, waveforms of the power supply voltage VDD, the reset pulse RST, and the transfer pulse TRF are shown. In addition, in FIG. 17, a potential of the vertical signal line 121 is shown. The horizontal direction of FIG. 17 represents time and the vertical direction of FIG. 17 represents a voltage.
For comparison, the potential of the vertical signal line 121 when the power supply voltage VDD does not change is indicated by a dashed line. When the power supply voltage VDD has changed in a signal read period, the potential of the vertical signal line 121 changes in accordance with a change in the power supply voltage VDD. In FIG. 17, an example in which the potential of the vertical signal line 121 decreases is shown. As a result, noise (an error) by ΔV occurs in the potential of the vertical signal line 121 as compared with when the power supply voltage VDD does not change in the signal read period.
The aforementioned noise due to the change in the power supply voltage is more significant in an endoscope system in which a solid-state imaging apparatus is mounted on a distal end of an endoscope and the power supply voltage or the like is supplied through a small-diameter cable.